A simple method for precise phase alignment between high-speed transceivers in FPGA

The on-chip clock network of a Field Programmable Gate Array (FPGA) usually only runs at a few hundred megahertz. For higher-speed off-chip data communication applications, the integrated high-speed Serial/Deserial (SerDes) transceiver can easily extend this limitation to a few gigahertz. However, the phase relationship between different SerDes transceivers is uncertain every time it is powered on, which greatly limits the high-speed digital control applications that require multiple SerDes transceivers for cooperative operation. This paper present a simple method to achieve phase alignment between multiple outputs of SeDes transceivers in FPGA. This method only takes a small amount of fabric logic resources, but has synchronization accuracy of 2.5 ps, and can be easily integrated into many applications such as high-speed control of gigahertz quantum key distribution.