2020Unpublished venueRequires access

Design of 100 W LDMOS based Power Amplifier for cellular applications

Ahmad Zakaria Ahmad, Ekta Aggrawal, Karun Rawat

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Abstract

This paper presents a design and implementation of a 100 W (50 dBm) power amplifier (PA) for the WCDMA base station application using laterally diffused metal oxide semiconductor (LDMOS) device which consists of two transistors integrated into a single package. To combine the output power of two transistors, active load combiner topology is adopted. This topology ensures that the optimum load impedance is maintained at the output of transistors, which provides high drain efficiency and high output power. A power amplifier is designed with this LDMOS transistor and its working is validated through measurement results. At 2.1 GHz, the measured gain of 10.8 dB, drain efficiency of 52.5% and output power more than 50 dBm is obtained. The effect of gate bias is also analyzed in measurement to show the relation of gain with gate bias variation.

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What this paper is about

This paper presents a design and implementation of a 100 W (50 dBm) power amplifier (PA) for the WCDMA base station application using laterally diffused metal oxide semiconductor (LDMOS) device which consists of two transistors integrated into a single package. To combine the output power of two transistors, active load combiner topology is adopted. This topology ensures that the optimum load impedance is maintained at the output of transistors, which provides high drain efficiency and high output power. A power amplifier is designed with this LDMOS transistor and its working is validated through measurement results. At 2.1 GHz, the measured gain of 10.8 dB, drain efficiency of 52.5% and output power more than 50 dBm is obtained. The effect of gate bias is also analyzed in measurement to show the relation of gain with gate bias variation.

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Available abstract

This paper presents a design and implementation of a 100 W (50 dBm) power amplifier (PA) for the WCDMA base station application using laterally diffused metal oxide semiconductor (LDMOS) device which consists of two transistors integrated into a single package. To combine the output power of two transistors, active load combiner topology is adopted. This topology ensures that the optimum load impedance is maintained at the output of transistors, which provides high drain efficiency and high output power. A power amplifier is designed with this LDMOS transistor and its working is validated through measurement results. At 2.1 GHz, the measured gain of 10.8 dB, drain efficiency of 52.5% and output power more than 50 dBm is obtained. The effect of gate bias is also analyzed in measurement to show the relation of gain with gate bias variation.

Key concepts: LDMOS, Amplifier, Transistor, Electrical engineering, RF power amplifier, Power-added efficiency, Power semiconductor device, Power gain

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