A 102dB-SFDR 16-bit Calibration-Free SAR ADC in 180-nm CMOS

A 16-bit successive approximation register analog-to-digital converter (ADC) is presented achieving superior spurious-free dynamic range (SFDR). This ADC uses VCM-based and binary-window digital-to-analog converter (DAC) switching schemes to improve the signal-to-noise and distortion ratio (SNDR). Moreover, a level-2 capacitor swapping scheme is proposed to improve the DAC linearity. A prototype ADC is fabricated in 180-nm CMOS and occupies an active area of 0.52 mm2. At 500 kS/s, it consumes a total power of 633 μW from a supply of 1.5 V. The measured differential and integral nonlinearity are -0.65/+0.9 and -2.7/+2.5 LSB, respectively. With 1 kHz input, the measured SNDR and SFDR are 77.9 dB and 102 dB, respectively. The effective number of bits is 12.7, equivalent to a Scherier figure-of-merit of 165 dB.