A 27mW 10-bit 125MSPS charge domain pipelined ADC

A low power 10-bit 125-MSPS analog-to-digital converter (ADC) with MOS bucket-brigade devices (BBDs) based charge-domain (CD) pipelined architecture is described. A PVT insensitive boosted charge transfer (BCT) circuit is used in the design of the 10-bit CD pipelined ADC, which largely conquers the PVT variations sensitivity of the existing BCT circuit and eliminates the common mode charge control circuit and simplifies the system complexity of the existing CD pipelined ADCs. The prototype ADC is realized in a 0.18 μm CMOS process without using any common mode charge control techniques, with the power consumption of only 27mW at 1.8V supply and active die area of 1.04mm2. The prototype ADC achieves spurious free dynamic range (SFDR) of 67.7 dB, signal-to-noise ratio (SNDR) of 57.3 dB and effective number of bits (ENOB) of 9.0 for a 3.79 MHz input at full sampling rate. Differential nonlinearity (DNL) is +0.5/-0.3 LSB and integral nonlinearity (INL) is +0.7/-0.55 LSB.