Educational Simulation of the RiSC Processor

In the context of courses related to “Architecture of microprocessors”, our educational objective is to make students understand the internal dynamic mechanism of processors. Since internal measurements are not possible on such devices, simulation is the only way. Hence, we have developed our own innovating simulator with a specific focus on student interactivity. We have chosen the RiSC16 processor because it is simple but complete and has been designed for educational purposes. The simulator we propose offers different opportunities. It allows the user to define its own programs in assembly language and to see graphically the corresponding internal dynamic behaviour of the processor (interactivity). Secondly, the visualization of the architecture of the RiSC16 is enhanced by the use of colours which change depending on the activity of the different blocks. Thirdly, stepping instruction by instruction allows the user to visualize the evolution of the content of memories and registers. Furthermore, the Java language has been chosen to implement our simulator. The modularity of this language makes it easy to adapt to other processors and let several perspectives open. The simulator has been tested in real laboratory conditions and showed to be quite helpful for the students.