A Floorplanning-Synthesis Methodology For Multiple Chip Module Design

The VLSI design automation is one of the most computational expensive and complicated processes with significant impact into computer chips manufacturing, especially at the physical layout design cycle. The recent VLSI evolution in multiple chip modules design has introduced new challenges at the physical layout steps (partitioning, floorplanning, placement, routing, compaction,etc). In this paper an efficient synthesis and floorplanning methodology for Multiple Chip Modules (MCM) design is discussed. The floorplanning-synthesis methodology is based on the efficient hierarchical cooperation of two formal languages (Scan, Geometria). Scan determines an acceptable planning by partitioning the floor area and defining a set of planning patterns on it. Geometria performs the synthesis placement part of the methodology by efficiently placing the chips modules and determining their routing.