An Efficient Ic On chip Test Framework To Embed Tsv Testing In Memory Bist Using Dynamic Technique

An end-to-end design of a built-in self-test (BIST) infrastructure for 3D-stacked ICs that facilitate the use of BIST at multiple stages of 3D integration. The proposed BIST design is distributed, reusable, and reconfigurable, hence it is attractive for both pre-bond and post-bond testing. We also provide support for translating a static BIST schedule into a set of BIST control instructions. The BIST design is validated using detailed simulations of the various operating modes. It results on synthetic stacks assess the impact of inserting BIST in these designs in terms of area, timing, and power overhead. Results show that the overhead due to BIST is negligible. It also formulate a test-scheduling problem that aims at minimizing test time under BIST-resource and power constraints, and use two algorithms based on bin packing for solving the problem.