A Single-Stage RISC-V Processor to Mitigate the Von Neumann Bottleneck

This paper presents a micro-processor which alleviates the major limitations on throughput caused by fetching instructions from program memory into the instruction register as a part of the von Neumann architecture. The proposed processor directly reads instructions from memory without latching into the instruction register. It enables to realize an efficient single stage operation, which is comparable to the pipelines. We experimentally show the effectiveness of the proposed configuration by implementing processors with the RISC-V instruction set architecture. Replacing the pipelines, the proposed processor promisingly maintains the efficiency even in applications including embedded systems which has many conditional branches.