The microarchitecture of a low power clustered register file for parallel processors

The requirement on number of register file ports in parallel processors poses a stringent challenge on register file design. The access time, power consumption and silicon area of the register file are strongly related to micro-architecture and the number of access ports. A clustered register file with global registers is presented in this work. Based on the simulation results using TSMC 18Onm CMOS technology, the proposed clustered register file with global registers exhibits up to 70% reduction in silicon area, 20% increase in operation frequency, 12% active power consumption reduction and 28% reduction in power delay product compared to the central register fde architecture.