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2019•Unpublished venueRequires access

Soft-Error-Tolerant Ultralow-Leakage 12T SRAM Bitcell Design

Jianwei Jiang, Dianpeng Lin, Jun Xiao, Shichang Zou

Open publisher page 2 citations

Abstract

This paper proposes a novel soft-error-tolerant ultralow-leakage 12T bitcell. Compared with all the other considered bitcells, the proposed cell saves 90.76% leakage power and 18.43% write access time on average. Simulation results verify the basic functions and single event upset (SEU) tolerance of the proposed. Hence, it is an excellent choice for highly reliable ultralow-leakage applications like the Internet of Things (IoT).

About this research paper

What this paper is about

This paper proposes a novel soft-error-tolerant ultralow-leakage 12T bitcell. Compared with all the other considered bitcells, the proposed cell saves 90.76% leakage power and 18.43% write access time on average. Simulation results verify the basic functions and single event upset (SEU) tolerance of the proposed. Hence, it is an excellent choice for highly reliable ultralow-leakage applications like the Internet of Things (IoT).

Why it matters

OpenAlex reports 2 citations for this work. Citation counts describe recorded attention and do not establish research quality.

Key contribution

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Method / approach

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Available abstract

This paper proposes a novel soft-error-tolerant ultralow-leakage 12T bitcell. Compared with all the other considered bitcells, the proposed cell saves 90.76% leakage power and 18.43% write access time on average. Simulation results verify the basic functions and single event upset (SEU) tolerance of the proposed. Hence, it is an excellent choice for highly reliable ultralow-leakage applications like the Internet of Things (IoT).

Key concepts: Leakage (economics), Soft error, Leakage power, Computer science, Static random-access memory, Embedded system, Electronic engineering, Reliability engineering

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