SRAM Cell Design to Improve Soft Error Tolerance

With the continuous technology scaling,the reduction of nodal capacitances and supply voltage have impacted severely the soft error rate of integrated circuits.Impacts of charged particle on the sensitive nodes could result in soft errors to modify the circuit functionality due to changing the configuration bits of SRAM based FPGA.Improving the soft error tolerance of SRAM would be one of the most efficient methods to enhance the reliability of the SRAM based FPGA,since the configuration data are stored in SRAM cells.One SRAM cell design,8T-SRAM,is proposed,which mainly aims at reducing the soft error rate in FPGA.The read/write speed,leakage power and the soft error tolerance of 6T-SRAM,ASRAM0 and 8T-SRAM are verified by using Spice simulation with the industrial 65nm CMOS techn-ology.Simulation result shows that the proposed SRAM design has better soft error immunity.The Soft Error Rate of 8T-SRAM is 44.20% less than that of the conventional 6T-SRAM.