A Systematic Delay and Power Dominant Carry Save Adder Design

This paper presents an efficient carry save adder design with multiplexer based adder architecture, instead of using ripple carry adder it replaces this ripple carry adder with modified adder to achieve effective output. Using this modified adder it can obtain reduced gate delay with low power consumption. The proposed design is from 8bit to 64 bit carry save adder. Where 64bit designs are most widely used in digital systems in present technology. As ripple carry adder is one of the most common type adder used in various designs, it has a long propagation delay and also consume more area and power. To reduce the gate delay and power the carry save adder is customized as i.e. carry save adder is cascaded with the ripple carry adder. In ripple carry adder first block is a half adder followed by the full adder chain and ends with a half adder. These full adders in first and second stage are replaced with modified full adder.