A Multi-Fault Dynamic Compaction Technique for Test Pattern Count Reduction

With the advance of IC fabrication technology, the manufacturing test data volume keeps growing because more fault models must be considered to ensure the product quality. In this paper, we develop a multi-fault dynamic compaction (MFDC) technique to reduce the number of test patterns by improving the pattern compaction efficiency. Compared to conventional single-fault dynamic compaction, the resulting test set is more compact, which lowers the test application time and cost. Simulation results on benchmark and industry circuits show an average of 18% pattern count reduction without fault coverage degradation.