MULTIPLE TARGET TEST GENERATORS FOR OPTIMIZING THE ATPG PROCESS TO REDUCE NUMBER OF TEST SETS

While defect oriented testing in digital circuits is a hard process, detecting a modeled fault more than one time has been shown to result in high defect coverage. Previous work shows that such test sets, known as multiple detector -detect test sets, are of increased quality for a number of common defects in deep sub-micrometer technologies. Method for multiple detect test generation usually produce fully specified test patterns. This limits their usage in a number of important applications such as low power test and test compression. This work proposes a systematic methodology for identifying a large number of bits that can be unspecified in a multiple detect test set, while preserving the original fault coverage. The experimental results demonstrate that the number of specified bits in, even compact, -detect test sets can be significantly reduced without any impact on the -detect property. Additionally, in many cases, the size of the test set is reduced. Current ATPG methods treat all faults independently from each other which limits the test compaction capability. We propose a new optimization SAT-based ATPG for compact test set generation with high fault coverage as well as a new retargeting stage for test set reduction. The ATPG is based on a novel Multiple-Target Test Generation (MTTG) formulation using optimization techniques. Robust SAT-based solving algorithms are leveraged to determine compatible fault groups which can be detected by the same test. The proposed technique can be used during initial compact test generation as well as a post-process to increase the compactness of existing test sets, e.g. generated by commercial tools, in an iterative manner.