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2018•Unpublished venueRequires access

Improvement of Endurance and Data-retention in 40nm TaOX-based ReRAM by Finalize Verify

Shouhei Fukuyama, Shinpei Matsuda, Ryutaro Yasuhara, Ken Takeuchi

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Abstract

This paper investigates Set/Reset endurance cycles utilizing Verify operation in order to extend the acceptable data-retention time of 40nm TaOXbased Resistive Random Access Memory (ReRAM). Applying Verify operation enhances data-retention time drastically at low Set/Reset cycles. However, as Set/Reset cycles with applying Verify operation increase, ReRAM-cell deteriorates and bit-error rate (BER) of low resistance state (LRS) increases [1]. To suppress this deterioration by Verify-stress, “Finalize_Verify” is proposed. As a result, the data-retention time of LRS is enhanced even at the high Set/Reset cycles. In addition, assuming to using error-correcting code (ECC), effect of ECC strength in Verify operation and Finalize_Verify operation is investigated.

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What this paper is about

This paper investigates Set/Reset endurance cycles utilizing Verify operation in order to extend the acceptable data-retention time of 40nm TaOXbased Resistive Random Access Memory (ReRAM). Applying Verify operation enhances data-retention time drastically at low Set/Reset cycles. However, as Set/Reset cycles with applying Verify operation increase, ReRAM-cell deteriorates and bit-error rate (BER) of low resistance state (LRS) increases [1]. To suppress this deterioration by Verify-stress, “Finalize_Verify” is proposed. As a result, the data-retention time of LRS is enhanced even at the high Set/Reset cycles. In addition, assuming to using error-correcting code (ECC), effect of ECC strength in Verify operation and Finalize_Verify operation is investigated.

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Available abstract

This paper investigates Set/Reset endurance cycles utilizing Verify operation in order to extend the acceptable data-retention time of 40nm TaOXbased Resistive Random Access Memory (ReRAM). Applying Verify operation enhances data-retention time drastically at low Set/Reset cycles. However, as Set/Reset cycles with applying Verify operation increase, ReRAM-cell deteriorates and bit-error rate (BER) of low resistance state (LRS) increases [1]. To suppress this deterioration by Verify-stress, “Finalize_Verify” is proposed. As a result, the data-retention time of LRS is enhanced even at the high Set/Reset cycles. In addition, assuming to using error-correcting code (ECC), effect of ECC strength in Verify operation and Finalize_Verify operation is investigated.

Key concepts: Resistive random-access memory, Data retention, Computer science, Optoelectronics, Materials science, Electrical engineering, Engineering, Voltage

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