A High Efficiency Asymmetric Doherty Power Amplifier Using Symmetric Devices for 5G Application

In this paper, an Asymmetric Doherty Power Amplifier using Symmetric Devices (ADSD) is proposed for 5G base-station application to improve the back-off efficiency and bandwidth. In the proposed ADSD structure, the main and auxiliary elementary power amplifier (PA) are designed to achieve optimal back-off efficiency and saturated power, respectively. In this way, the overall performance can be improved while the drawbacks caused by utilizing asymmetric devices in conventional asymmetric Doherty Power Amplifier (DPA) are overcome. To verify the proposed theory and design method, an example 3.4-3.6GHz broadband ADSD is designed and fabricated using two 30-Watt transistors. According to the measured results, the ADSD exhibits 50.6%-57.3% Drain Efficiency (DE) at 6-dB power backoff and 54%-62% at saturation over the 200MHz designed bandwidth. Moreover, when stimulated using a 100MHz, 7.5 dB PAPR LTE signal at 3.5 GHz, the fabricated ADSD exhibits 45% average efficiency and 39 dBm output power after linearization while maintaining the Adjacent Channel Leakage Ratio (ACLR) below −47dBc.