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2018•Unpublished venueRequires access

A Bit Cycling Method for Improving the DNL/INL in Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC)

Hua Fan, Chen Wang, Hailiang Xiong, Quanyuan Feng, Dagang Li, Kelin Zhang, Xiaopeng Diao, Lishuang Lin, Hadi Heidari

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Abstract

This paper presents a bit cycling method to improve the max root mean square (rms) value of differential nonlinearity (DNL) and the max rms value of integral nonlinearity (INL) for successive approximation register (SAR) analog-to-digital converter (ADC). Neither an additional DAC nor any complex correction algorithm are needed in this work, it is only necessary to switch between two different bit cycling modes, then it is possible to avoid the accumulation error of the capacitor mismatch caused by the same codes, so as to achieve the purpose of upgrading DNL and INL, and finally to improve the static linearity of SAR ADC.

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What this paper is about

This paper presents a bit cycling method to improve the max root mean square (rms) value of differential nonlinearity (DNL) and the max rms value of integral nonlinearity (INL) for successive approximation register (SAR) analog-to-digital converter (ADC). Neither an additional DAC nor any complex correction algorithm are needed in this work, it is only necessary to switch between two different bit cycling modes, then it is possible to avoid the accumulation error of the capacitor mismatch caused by the same codes, so as to achieve the purpose of upgrading DNL and INL, and finally to improve the static linearity of SAR ADC.

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Available abstract

This paper presents a bit cycling method to improve the max root mean square (rms) value of differential nonlinearity (DNL) and the max rms value of integral nonlinearity (INL) for successive approximation register (SAR) analog-to-digital converter (ADC). Neither an additional DAC nor any complex correction algorithm are needed in this work, it is only necessary to switch between two different bit cycling modes, then it is possible to avoid the accumulation error of the capacitor mismatch caused by the same codes, so as to achieve the purpose of upgrading DNL and INL, and finally to improve the static linearity of SAR ADC.

Key concepts: Successive approximation ADC, Differential nonlinearity, Integral nonlinearity, Shaping, Digital-to-analog converter, Linearity, Capacitor, Computer science

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