A 10‐bit 1GSample/s hybrid digital‐to‐analog converter with a modified thermometer decoder in 65‐nm CMOS technology

Abstract This paper proposes a new 10‐bit 1GS/s digital‐to‐analog converter (DAC). In the proposed DAC configuration, a beneficial combination of differential resistor ladder and current sources is utilized to attain a significant reduction of the number of unit current sources. Therefore, the suggested 10‐bit DAC is constructed based on only 21 current sources and 64 unit resistors, which results in a considerable decrease regarding the occupied area and power consumption. Also, a modified 4‐bit thermometer decoder using a low number of transistors, based on SET‐RST D flip‐flops (SR‐DFFs), is offered to drive the unit current sources synchronously. The proposed DAC is simulated in 65‐nm Complementary metal oxide semiconductor (CMOS) technology. The postlayout simulation results indicate the better integral nonlinearity (INL) and differential nonlinearity (DNL) parameters than 0.3 least significant bit (LSB) and 0.6 LSB, respectively. Based on achieved results, the proposed DAC consumes 9.31 mW using a single supply voltage of 1.2 V. Moreover, the spurious‐free dynamic range (SFDR) is above 57 dB over 600‐MHz Nyquist bandwidth, by considering 0.0134 mm2its occupied area.