Design and FPGA implementation of a high speed and low power 64-bit adder

In this thesis, two new adder architectures are presented which introduce new arrangement for the node connections in the structure of parallel prefix adders. The first proposed adder was obtained by combining the vertical first half of the Ladner-Fischer adder and the second half of the Brent-Kung adder so that the number of steps in the critical pathway and, as a result, the propagation delay were reduced. This improvement was accompanied by a slight increase in power consumption, but ultimately the value of the PDP (Power-Delay Product) was reduced. The efficiency of this adder improves with larger number of the input bits. The results of simulations For the firot proposed adder have shown that the value of the PDP was reduced about 6% in 16 bit, 18% in 32 bit, and 40% in 64 bit input. In the second proposed adder, by vertical integration of the first half, adder of the Kogge-Stone adder and the second half of the Sklansky adder the number of nodes and connections in the second half and also the power consumption of this architecture has been reduced. The amount of fan-out capacity has also decreased in compared to the Sklansky adder. The results of the simulations for the PDP of the second proposed adder show an improvement of about 17% for 16-bit, 21% for 32-bit and 25% for the 64-bit inputs. All simulations have been performed in CMOS 45nm technology and with the Hspice software. The result of the simulations have shown that the proposed adders are better than traditional tree adders.