PROPAGATION DELAY BASED COMPARISON OF

An intelligent full adder circuit is simulated using Cadence Virtuoso Analog Design version 6.0. The complementary property between sum and carry for most of the input combination is considered for reducing the number of transistors in the full adder circuit. The parameters such as the Power consumption, Delay and Power Delay Product (PDP) are improved in the proposed CMOS full adder than the conventional CMOS full adder. The size of the chip and the number of transistors are greatly reduced with the proposed circuit. From the single bit full adder module, other parallel adder circuits such as Ripple carry Adder, Carry Look Ahead Adder, Carry Save Adder, Carry Increment adder, Carry Skip Adder, Carry Select Adder and Carry By-pass Adder are simulated. The worst-case gate delay in each case is measured and compared with other adders.