Plane-Pair PEEC Modeling for Package Power Layer Nets with Inductance Extraction

Recent FPGAs and CPUs consume significant power, and a low impedance power distribution network (PDN) is critical to get a robust performance. The decoupling capacitors in package usually provide charge for mid frequency switching currents, from tens of MHz to a few hundreds of MHz. The effectiveness of these capacitors are limited by the inductance associated with the current loop. Although commercial tools can estimate the PDN impedance, they do not generate a physics-based circuit which provides insight of where the inductance collects. In this short paper, a plane pair partial element equivalent circuit (PPP) method is applied to extract the inductance of the power layers on package. The method is validated by comparing with the cavity model and a commercial tool. The extracted inductance can be used to generate a physics based circuit model.