A Novel 2b/Cycle Time And Voltage Based Conversion Technique In SAR ADC

This paper proposes a 2b/cycle time and voltage based conversion technique in successive approximation register analog-to-digital converter (SAR ADC). At low supply voltage there will be a significant difference in comparator decision time for different input voltages. By utilizing the information of decision time, this ADC achieves 2b/cycle quantization to improve the conversion speed. To validate the concept, a 10-bit SAR ADC is designed using 130 nm CMOS process with 0.5 V supply voltage. Simulation results shows the ADC achieve SNDR (signal-to-noise distortion ratio) of 60.26 dB, corresponding to an ENOB (effective number of bits) of 9.72 bits.