A study of 10-bit 2-MS/s Successive Approximation Register ADC with low power in 180nm technology

This paper presents Successive Approximation Register (SAR) ADC design in 180nm TSMC technology. The ADC can provide a high effective number of bits (ENOB), high speed and low power. At a 1.8-V supply and 2 MS/s, our design achieves an SNDR of 59.5 dB, ENOB 9.59 bit and consumes 1.17 mW, resulting in a figure of merit (FOM) of 759 fJ/conversion-step. To attain the mentioned results, the SAR architecture is proposed to use SAR ADC fully differential with S/H circuit, Capacitive DAC, Dynamic latch comparator, SAR Logic.