Retracted: 4x4 bit Vedic multiplier using 13T hybrid full adder in 90 nm CMOS technology

In this paper, a 4x4 bit Vedic multiplier has been designed using the combination of Urdhva Triyakbyam Sutra and 13T hybrid full adder (HFA). This algorithm satisfied the requirement of a fast multiplication operation, which reduced the number of partial products compared to other techniques. The multiplier is simulated using Synopsys Custom Tools with General Process Design Kit (GPDK) of 90 nm CMOS technology. With a 1 V voltage supply, this 4x4 Vedic multiplier is able to produce a full output voltage swing utilizing a power consumption of 0.2015 mW, delay of 376 ps and compact area which only consumed 3100 µm 2 . With the combination of HFA and Vedic mathematics, a new combination of multiplier method with low power and low delay has been successfully produced.