Automated Generation of Synchronous Formal Models from SystemC Descriptions

SystemC is one of the most popular electronic system-level design language and it is embraced by a growing community that seeks to move to a higher level of abstraction. It lacks however a standard way of integrating formal methods and formal verification techniques into a SystemC design flow. In this paper, we show how SystemC descriptions are automatically transformed into the formal synchronous language Signal, while conserving the original structure and enabling the application of formal verification techniques. Signal provides a simple semantics of concurrency and time, and allows verification with an existing theorem prover and model checker. The approach that we propose consists of two steps: the extraction of the structure and the transformation of the behavior. In the first step, SystemC model is analyzed and the structural information is extracted. In the second step, for each SystemC module, the corresponding Signal behavior is generated and filled into the already prepared Signal structure.