2017•Unpublished venueRequires access

Design of ALU using dual mode logic with optimized power and speed

Neetika Yadav, Preeti Kumari

Open publisher page 12 citations

Abstract

In this paper, a design of an Arithmetic Logic Unit (ALU) by taking advantage of the concept of dual mode logic (DML) technique has been implemented. ALU is one of the most significant component of any computing system be it microprocessors, embedded structures or any other computational device. In this, ALU consists of 4×1 multiplexer, 2-input and unit, 2-input or unit, 2-input exor unit and a full adder designed to implement logic operations, such as and, or, exor and arithmetic operation of addition using a full adder. DML technique has been used for designing of multiplexer, full adder, and unit, or unit and exor unit which are then associated to realize the DML based ALU. Power of static CMOS ALU and delay of domino ALU architecture were calculated which were then compared with static mode and dynamic mode of DML based ALU respectively. This is designed and simulated using Mentor Graphics Pyxis Schematic Tool with 1.8 V supply voltage and 180 nanometer(nm) technology.

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What this paper is about

In this paper, a design of an Arithmetic Logic Unit (ALU) by taking advantage of the concept of dual mode logic (DML) technique has been implemented. ALU is one of the most significant component of any computing system be it microprocessors, embedded structures or any other computational device. In this, ALU consists of 4×1 multiplexer, 2-input and unit, 2-input or unit, 2-input exor unit and a full adder designed to implement logic operations, such as and, or, exor and arithmetic operation of addition using a full adder. DML technique has been used for designing of multiplexer, full adder, and unit, or unit and exor unit which are then associated to realize the DML based ALU. Power of static CMOS ALU and delay of domino ALU architecture were calculated which were then compared with static mode and dynamic mode of DML based ALU respectively. This is designed and simulated using Mentor Graphics Pyxis Schematic Tool with 1.8 V supply voltage and 180 nanometer(nm) technology.

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Available abstract

In this paper, a design of an Arithmetic Logic Unit (ALU) by taking advantage of the concept of dual mode logic (DML) technique has been implemented. ALU is one of the most significant component of any computing system be it microprocessors, embedded structures or any other computational device. In this, ALU consists of 4×1 multiplexer, 2-input and unit, 2-input or unit, 2-input exor unit and a full adder designed to implement logic operations, such as and, or, exor and arithmetic operation of addition using a full adder. DML technique has been used for designing of multiplexer, full adder, and unit, or unit and exor unit which are then associated to realize the DML based ALU. Power of static CMOS ALU and delay of domino ALU architecture were calculated which were then compared with static mode and dynamic mode of DML based ALU respectively. This is designed and simulated using Mentor Graphics Pyxis Schematic Tool with 1.8 V supply voltage and 180 nanometer(nm) technology.

Key concepts: Arithmetic logic unit, Adder, Multiplexer, Computer science, Domino logic, Schematic, Computer hardware, Logic gate

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