Yong Surk Lee, Peter Joh, Jae Hee You, Kyu Tae Park
Abstract
A CMOS arithmetic logic unit is presented with a minimum number of transistors and high speed arithmetic operations. Multiple carry chain adders, a novel 1 bit adder, are used in a carry select adder. The carry chain adder has a high degree of shared gates with a low propagation delay.
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A CMOS arithmetic logic unit is presented with a minimum number of transistors and high speed arithmetic operations. Multiple carry chain adders, a novel 1 bit adder, are used in a carry select adder. The carry chain adder has a high degree of shared gates with a low propagation delay.
Key concepts: Adder, Arithmetic, Carry (investment), Arithmetic logic unit, Serial binary adder, Carry-save adder, Pass transistor logic, Logic gate