Proposal for Multi-Gate Spin Field-Effect Transistor
Gefei Wang, Zhaohao Wang, Xiaoyang Lin, Jacques‐Olivier Klein, Weisheng Zhao
Abstract
Gefei Wang, Zhaohao Wang, Xiaoyang Lin, Jacques‐Olivier Klein, Weisheng Zhao
Abstract
The conductivity of spin field-effect transistor (spin-FET) can be modulated by controlling the spin degree of freedom; therefore, emerging low-power applications can be explored. In this paper, we propose a novel device called multi-gate spin-FET where multi-gate voltages can successively modulate the spin of the electrons. Various logic functions can be implemented with multi-gate spin-FET by setting the appropriate channel lengths. First, we present an electrical model of the multi-gate spin-FET which considers the physical mechanisms and the fitting of experimental results. The availability of the electrical model is validated by the dc simulation. Afterward, typical logic circuits are designed with the multi-gate spin-FET, including NAND gate, XOR gate, full adder, and a representative three-input logic gate. Transient simulation results validate the functional behaviors of these logic circuits. Finally, based on an analysis of power consumption, we conclude that the multi-gate spin-FET is a more energy-efficient device compared with the conventional CMOS FET.
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The conductivity of spin field-effect transistor (spin-FET) can be modulated by controlling the spin degree of freedom; therefore, emerging low-power applications can be explored. In this paper, we propose a novel device called multi-gate spin-FET where multi-gate voltages can successively modulate the spin of the electrons. Various logic functions can be implemented with multi-gate spin-FET by setting the appropriate channel lengths. First, we present an electrical model of the multi-gate spin-FET which considers the physical mechanisms and the fitting of experimental results. The availability of the electrical model is validated by the dc simulation. Afterward, typical logic circuits are designed with the multi-gate spin-FET, including NAND gate, XOR gate, full adder, and a representative three-input logic gate. Transient simulation results validate the functional behaviors of these logic circuits. Finally, based on an analysis of power consumption, we conclude that the multi-gate spin-FET is a more energy-efficient device compared with the conventional CMOS FET.
Key concepts: NAND gate, Logic gate, Gate equivalent, AND-OR-Invert, Spin transistor, Pass transistor logic, Adder, AND gate