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Ultra low voltage and, nor and XOR CMOS gates

Yngvar Berg, Omid Mirmotahari, Snorre Aunet

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Abstract

In this paper we present NAND, NOR and XOR gates exploiting the ultra low-voltage (ULV) CMOS logic style [1] [2]. There are two kinds of NAND and NOR gates available using the ULV logic style; straightforward gates resembling complementary CMOS and threshold holdgates. In addition to NAND and NOR gates we present a minority three gate and an XOR ULV gate. The electrical characteristics of these two approaches are discussed with a focus on delay and noise margins. Simulated data assuming a 90 nm CMOS process is included.

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What this paper is about

In this paper we present NAND, NOR and XOR gates exploiting the ultra low-voltage (ULV) CMOS logic style [1] [2]. There are two kinds of NAND and NOR gates available using the ULV logic style; straightforward gates resembling complementary CMOS and threshold holdgates. In addition to NAND and NOR gates we present a minority three gate and an XOR ULV gate. The electrical characteristics of these two approaches are discussed with a focus on delay and noise margins. Simulated data assuming a 90 nm CMOS process is included.

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Available abstract

In this paper we present NAND, NOR and XOR gates exploiting the ultra low-voltage (ULV) CMOS logic style [1] [2]. There are two kinds of NAND and NOR gates available using the ULV logic style; straightforward gates resembling complementary CMOS and threshold holdgates. In addition to NAND and NOR gates we present a minority three gate and an XOR ULV gate. The electrical characteristics of these two approaches are discussed with a focus on delay and noise margins. Simulated data assuming a 90 nm CMOS process is included.

Key concepts: NAND gate, AND-OR-Invert, CMOS, XOR gate, Logic gate, Pass transistor logic, Computer science, Electronic engineering

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