A DDS-Driven ADPLL Chirp Synthesizer with Ramp-Interpolating Linearization for FMCW Radar Application in 65nm CMOS

The paper presents a wideband, low-power chirp synthesizer for Ku-band FMCW radars. The DDS-driven ADPLL chirp synthesizer generates chirps up to 2GHz bandwidth. A low-power DDS is employed to generate a stepped reference frequency for ADPLL to ensure the long term chirp linearity, while the ADPLL fulfill the ramp-interpolating linearization by generating a narrow band chirp within the step frequency. The entire chirp benefits from the phase domain modulation and mitigates ADPLL loop bandwidth variation to achieve high linearity and low power. A novel adaptive ramping control scheme is adopted to ensure the chirp rate is constant after combining the narrow band chirp segments. By this two-stage chirp generation, a 2-GHz chirp is achieved with low relative frequency RMS error. Fabricated in a 65nm CMOS, the synthesizer generates a wideband chirp from 13.9GHz to 15.9GHz with configurable rate from 0.25 to 4GHz/ms, and consumes 53.8mW.