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2017•Unpublished venueRequires access

Design of power efficient hybrid flash-successive approximation register analog to digital converter

Priyanka Dhage, Pradnya R. Jadhav

Open publisher page 4 citations

Abstract

The need for a high speed and low power ADC is very essential for various applications. This paper presents a new hybrid analog-to-digital convertor (ADC) combining a capacitive digital-to-analog (CDAC) based multi-bit/cycle successive approximation (SAR) ADC with a flash ADC. As portable terminals demand long battery and high sampling rate. Handheld equipment's for wireless like WI-FI and WI-MAX or cellular communication systems like WCDMA, CDMA 2000 and TDSCDMA requires power efficient, moderate resolution and high sampling rate ADC's. By using the proposed scheme, we achieved not only high-speed conversion, but also more efficient digital-error-correction (DEC). The flash-SAR ADC is simulated in 90nm technology using CMOS process.

About this research paper

What this paper is about

The need for a high speed and low power ADC is very essential for various applications. This paper presents a new hybrid analog-to-digital convertor (ADC) combining a capacitive digital-to-analog (CDAC) based multi-bit/cycle successive approximation (SAR) ADC with a flash ADC. As portable terminals demand long battery and high sampling rate. Handheld equipment's for wireless like WI-FI and WI-MAX or cellular communication systems like WCDMA, CDMA 2000 and TDSCDMA requires power efficient, moderate resolution and high sampling rate ADC's. By using the proposed scheme, we achieved not only high-speed conversion, but also more efficient digital-error-correction (DEC). The flash-SAR ADC is simulated in 90nm technology using CMOS process.

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Available abstract

The need for a high speed and low power ADC is very essential for various applications. This paper presents a new hybrid analog-to-digital convertor (ADC) combining a capacitive digital-to-analog (CDAC) based multi-bit/cycle successive approximation (SAR) ADC with a flash ADC. As portable terminals demand long battery and high sampling rate. Handheld equipment's for wireless like WI-FI and WI-MAX or cellular communication systems like WCDMA, CDMA 2000 and TDSCDMA requires power efficient, moderate resolution and high sampling rate ADC's. By using the proposed scheme, we achieved not only high-speed conversion, but also more efficient digital-error-correction (DEC). The flash-SAR ADC is simulated in 90nm technology using CMOS process.

Key concepts: Successive approximation ADC, Flash ADC, Computer science, Analog-to-digital converter, Electronic engineering, Flash (photography), CMOS, Effective number of bits

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