Design of an efficient RF-DC voltage multiplier for RF Energy Harvesting Applications

In this paper, a RF-DC voltage multiplier is presented to efficiently convert RF signals to DC voltages. The proposed circuit uses an internal threshold voltage cancellation (IVC) scheme with auxiliary block to reduce the threshold voltage of forward-biased transistors and minimizes the reverse leakage current of the reverse-biased by dynamically controlling the gate-source voltage of the transistors in the main rectification chain. The proposed circuit is designed in 0.18 um CMOS technology. A three-stage voltage multiplier results in a maximum power conversion efficiency (PCE) of 49.1% at input power level of 0 dBm and at frequency of 900 MHz. The proposed circuit produces an output voltage of 4.94 V at 50 KΩ load.