A Study of Some Design Choices for Improving the Performance of a Shared Cache System

Abstract : Processors with private caches have usually been assumed in the study of multi processor systems, particularly when the number of processor is large. A private cache organization allows a processor to access only its own cache and some mechanism is required to maintain data coherence between all the caches. A number of solutions for the coherence problem have been proposed but all impose some degree of performance penalty on the system. For a medium size multi processor, e.g. where the number of processor is less than or equal to (16), an alternative scheme is to share a single cache among all the processors. A shared cache organizations does not generally require a coherence mechanism and potentially offers better performance for accessing shared data. However, when multiple processors attempt to access the cache within the same cache, conflicts occur such that one or more processors must wait for cache service. Furthermore, due to multiple reference streams, how a shared cache handles cache misses can have an important effect on system performance. This thesis discusses the organization of a shared cache system and looks at the effect on its performance when the number of cache banks is increased and when buffer queues are added. In particular, by evaluating shared cache access conflicts and cache miss effects, we look at how these changes affect multi-processor performance. Keywords: Multiprocessors; Computer architecture; Computer programs; Simulation.