Architecture support for synchronization and communications in multi-core processors

The quest for greater computational power is never-ending, and exploiting parallelism is central to this quest. Recently, the architectural trend has shifted from improving single-threaded application performance, traditionally achieved by exploiting instruction level parallelism (ILP), to improving multithreaded application performance by supporting thread level parallelism (TLP). Thus, multi-core processors that are built by incorporating two or more processor cores on a single die have been increasingly popular. To achieve concurrent execution of threads on multi-core processors, applications must be explicitly restructured to exploit parallelism, either by programmers or compilers. However, conventional parallel programming models may introduce overhead due to synchronization and communications among threads in multithreaded applications. Even though there are shared resources among the processor cores, there is no explicit synchronization and communications support for multithreaded applications to take advantage of the proximity between these cores. Busy waits may introduce synchronization overhead in terms of cache coherence traffic and miss rates. Register-Based Synchronization ( RBS) uses hardware registers efficiently to provide synchronization support in multi-core processors, and reduces coherence traffic and miss rates, and helps power savings. In addition, demand-based data transfers among threads in multithreaded applications may add to the communication latency. Prepushing is a software controlled data forwarding technique to provide communications support in multi-core processors. It sends data to destination's cache before it is demanded, eliminating cache misses in the destination's cache as well as reducing the cache coherence traffic on the bus. Furthermore, the location of shared data has a crucial effect on performance because if the requested data is found in the shared cache rather than a remote cache or main memory, the data access latency will be less resulting in performance improvement. Software Controlled Eviction (SCE) improves shared cache communications by placing shared data in shared caches so that it can be found in a much closer location than remote caches or main memory. Simulation results show significant performance improvement with the addition of these architecture optimizations in multi-core processors.