Efficient implementation of FPGA based on Vivado High Level Synthesis

The Xilinx Vivado High Level Synthesis (HLS) transforms a C specification into a register transfer level (RTL) implementation that can be synthesized into a Xilinx field programmable gate array (FPGA). It refers to the automatic integrated initially with C, C ++ or System C language to describe digital designs. Using HLS to explore all possibilities, analysis and performance characteristics of the area, and finalize a program to implement algorithms on FPGA chip. An example of a filter in this paper described the use of HLS to implement on FPGA quickly and efficiently.