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2002•Proceedings of WESCON '94Requires access

Logic synthesis for programmable logic design

M. Ligthart

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Abstract

This paper presents a logic synthesis system for field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs) based on either the Verilog HDL or VHDL. It describes aspects of synthesis and optimization specific to FPGAs and CPLDs, in contrast to CMOS gate-arrays. Particular attention is paid to architecture specific optimization, both on register transfer and logic level. The concept of the design methodology is proven by a real-world implementation of an actual design.>

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What this paper is about

This paper presents a logic synthesis system for field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs) based on either the Verilog HDL or VHDL. It describes aspects of synthesis and optimization specific to FPGAs and CPLDs, in contrast to CMOS gate-arrays. Particular attention is paid to architecture specific optimization, both on register transfer and logic level. The concept of the design methodology is proven by a real-world implementation of an actual design.>

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Available abstract

This paper presents a logic synthesis system for field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs) based on either the Verilog HDL or VHDL. It describes aspects of synthesis and optimization specific to FPGAs and CPLDs, in contrast to CMOS gate-arrays. Particular attention is paid to architecture specific optimization, both on register transfer and logic level. The concept of the design methodology is proven by a real-world implementation of an actual design.>

Key concepts: Verilog, VHDL, Register-transfer level, Computer architecture, Logic synthesis, Programmable Array Logic, Field-programmable gate array, Computer science

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