DESIGN AND IMPLEMENTATION OF 32 BITMULTIPIER USING VEDIC MATHAMATICS

In this paper, a novel multiplier architecture based on ROM approach using Vedic Mathematics is proposed. This multiplier's architecture is similar to that of a Constant Coefficient Multiplier (KCM). However, for KCM one input is to be fixed, while the proposed multiplier can multiply two variables, three variables and so on. The proposed multiplier of 32-bit is implemented on a Spartan xc5s500e III FPGA, it is fast ,less power consumption as compared with Array Multiplier and Urdhava Multiplier for 32-bit cases.