Design and Synthesis of Low Power, High Speed 5th Order Digital Decimation Filter for Sigma- Delta Analog to Digital Converter

The paper presents the design of a 5thorder digital decimation filter using a 5thorder Cascaded Integrator Comb (CIC) filter and two halfband Finite Impulse Response (FIR) filters in cascade. The output of the CIC filter is downsampled by factor of 8, 16, 32 or 64. The CIC filter, designed using recursive and non-recursive algorithms, is constructed using a cascade of codec, integrator, downsampler and differentiator. The integrators work at input clock frequency of 100 MHz while the differentiators work at a downsampled frequency. The two halfband FIR filters are used as droop correction filters to uplift the signal from CIC filter. Decimation filter is designed and synthesized using Verilog HDL 90 nm technology. The synthesis of the non-recursive algorithm with a decimation factor of 64 resulted in power consumption of 38.397mW, a delay of 1.823ns and consumed 114 units of cell area. The CIC filter designed using non-recursive algorithm reduces the area and power by 7 times and 5 times respectively compared to recursive algorithm. The non-recursive CIC filter is three times faster compared to the recursive CIC filter.