A fast carry chain adder using Instantiation design entry on Virtex-5 FPGA

This paper presents the fast carry chain adder using Instantiation design entry which facilitates the direct design of the components through exact placement of the individual blocks in FPGA. The basic n-bit adder is divided into n/3 number of ripple carry adders with carry inputs generated from separate carry generator. The carry generator is designed on LUT by using all the six inputs with 100% utilization. A 64 bit adder is designed and observed that the proposed scheme is 120.11% and 31.05% faster than the standard carry chain adder and DSP based adder respectively.