Design and analysis of low run-time leakage in a 10 Transistors full adder in 45nm technology

In this paper the different topologies of one bit full adders including the most interesting of one proposed is analysed and compared for peak leakage,average leakage, peak power and average power. The investigation carried out with properly defined simulation runs on a cadence environment using 45 nm technology. The proposed 10 Transistor full adder has consumed 57% of average power of conventional CMOS logic circuit with 28 transistors. Where as in average leakage it has consumed 67% of average leakage power of conventional CMOS with 28 Transistors. The peak leakage and peak power of proposed 10 Transistors are 67% and 70% respectively of conventional 28 Transistors CMOS logic. The proposed full adder has only 10 Transistors.This saves silicon area.