New designs of 14-transistor PPM adder

In this paper, we propose improved designs of full adders, known as plus-plus-minus (PPM) adders, for redundant binary (RB) number systems applications. The proposed two PPM adder designs use 14 transistors and are derived from new algorithms. They achieve reduction in the time delay, power consumption, and chip area, compared to currently available designs. Furthermore, the proposed 14-transistor adders have been used to build two efficient designs of on-line radix-2 redundant multipliers. All the proposed designs have been implemented using 0.18 mum CMOS technology. The implementation results show that the proposed PPM adders have significant reduction in both power consumption and time delay compared to the 24-transistor PPM adder