Design of Arbiter for DDR2 memory controller and interfacing frontend with the memory through backend

The aim of this is to design Arbiter for DDR2 memory controller and interfacing frontend with the memory of size 1k×64 through backend to perform write and read operations. The aim of this study was to investigate the different problems associated with the design of DDR2 memory controller. This work provides a brief overview of the DDR2 SDRAM device features and a detailed explaination of the controller operation when interfacing to highspeed DDR2 memories. It also explains the backend user interface to the controller. The DDR2 SDRAM Memory Controller IP Core provides a high performance interface to DDR2 SDRAM devices. The DDR2 SDRAM Memory Controller IP Core accepts read and write commands using a simple client Interface and translate these requests to the command sequences required by DDR2 SDRAM devices. Hence the speed and bandwidth of the system memory controls application performance. Over the years, the need for greater memory bandwidth has driven system memory evolution from asynchronous DRAM technologies to high-bandwidth synchronous DRAM (SDRAM), and nally to today's Double Data Rate 2 (DDR2) SDRAM technologies. DDR2 memory can send data on both the rising and falling edges of the processor's clock cycles. The result of this study highlights write and read operations to the memory. The biggest design challenge is to implement the sampling of data being read from the DDR2 since the data will switch even faster than for the DDR case.