Novel powergating technique for reconfigurable FPGA architectures

To mitigate the total power consumption in any circuit, ASICs or FPGAs, various conventional power gating techniques has been adopted depending upon the need of the application, dynamically controlled power gating procedure is one such power gating technique which can be used to reduce the total leakage power consumption of the circuit during the runtime. It can be applied on the real time application oriented architecture and high efficient power analysis can be done on the circuit. This helps in overall energy saving applications which includes modules having long idle time. In this paper, we propose a novel power gating technique for the reconfigurable architectures which exploit the idleness of the block during its runtime. The proposed novel power gating technique is proven to consume lesser area, delay, power when compared with the dynamically controlled power gating techniques.