A 0.7-V Clock-gating Cell with Power Gating Technology and 1.56-pA Sleep Power

In digital circuits, dynamic power consumption caused by clock switching occupies a large part of the total power consumption. Dynamic power consumption can be effectively reduced by using clock-gating technology. In this work, a clock-gating cell is proposed with sleeping mechanism under 0.7 V supply. Power gating is used to decrease the static power. The proposed cell can be used in circuit with frequency up to 1MHz typically. Compared to existing design, this work stands out for lower leakage current of 1.56 pA, which is suitable for circuits in low frequency where low power standard cell library is required.