A Coarse-grained asynchronous data-driven design flow

As the synchronous circuit design is facing some limits, such as the power wall and the clock skew problem, the asynchronous circuit design is approaching a revival. This paper presents a coarse-grained data-driven design flow for asynchronous circuits, which aims at both performance and design efficiency. Based on a set of data-driven components, pipelined asynchronous circuits can be efficiently constructed. We optimize the circuits by combining components to form coarse-grained pipelines. Experimental results on an asynchronous pipelined 32-bit iterative multiplier show the efficiency of our design flow.