2012Unpublished venueRequires access

A 34 Gbps data transmission system with FPGAs embedded transceivers and QSFP+ modules

Roberto Ammendola, A. Biagioni, Ottorino Frezza, Francesca Lo Cicero, A. Lonardo, Pier Stanislao Paolucci, Davide Rossetti, Andrea Salamon, Francesco Simula, Laura Tosoratto, P. Vicini

Open publisher page 3 citations

Abstract

APEnet+ is our custom developed PCIe gen2 board based on an Altera Stratix IV FPGA. We demonstrate reliable usage of Altera's embedded transceivers coupled with QSFP+ (Quad Small Form Pluggable) technology. QSFP+ standard defines a hot-pluggable transceiver available in copper or optical cable assemblies for an aggregated bandwidth of up to 40 Gbps. We use embedded transceivers in a 4 lane configuration, each one capable of 8.5 Gbps, for an aggregate bandwidth of 34 Gpbs per link. On Stratix IV 290 we can place up to 6 bidirectional links, together with a PCIe gen2 ×8 hard IP. We describe design and implementation of this data transmission system.

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What this paper is about

APEnet+ is our custom developed PCIe gen2 board based on an Altera Stratix IV FPGA. We demonstrate reliable usage of Altera's embedded transceivers coupled with QSFP+ (Quad Small Form Pluggable) technology. QSFP+ standard defines a hot-pluggable transceiver available in copper or optical cable assemblies for an aggregated bandwidth of up to 40 Gbps. We use embedded transceivers in a 4 lane configuration, each one capable of 8.5 Gbps, for an aggregate bandwidth of 34 Gpbs per link. On Stratix IV 290 we can place up to 6 bidirectional links, together with a PCIe gen2 ×8 hard IP. We describe design and implementation of this data transmission system.

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Available abstract

APEnet+ is our custom developed PCIe gen2 board based on an Altera Stratix IV FPGA. We demonstrate reliable usage of Altera's embedded transceivers coupled with QSFP+ (Quad Small Form Pluggable) technology. QSFP+ standard defines a hot-pluggable transceiver available in copper or optical cable assemblies for an aggregated bandwidth of up to 40 Gbps. We use embedded transceivers in a 4 lane configuration, each one capable of 8.5 Gbps, for an aggregate bandwidth of 34 Gpbs per link. On Stratix IV 290 we can place up to 6 bidirectional links, together with a PCIe gen2 ×8 hard IP. We describe design and implementation of this data transmission system.

Key concepts: PCI Express, Stratix, Transceiver, Field-programmable gate array, Computer science, Embedded system, Bandwidth (computing), Data transmission

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