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A 3-bit 20GS/s interleaved flash analog-to-digital converter in SiGe technology

Yuan Yao, Xuefeng Yu, Dayu Yang, Foster Fa Dai, David Irwin J., Richard C. Jaeger

Open publisher page 10 citations

Abstract

A 3-bit analog-to-digital converter (ADC) for software defined radio applications that can work at a sampling rate of 20 GS/s is presented in this paper. In order to operate at Ku-band, two flash current mode logic (CML) ADCs are time-interleaved to achieve a 20 GHz sampling rate. A 3-bit current-steering digital-to-analog converter (DAC) is also designed for testing the high-speed ADC. The ADC-DAC RFIC is implemented in a 0.12 mum SiGe technology and occupies an area of 1.5 times 1.7 mm2. The total power consumption for the entire ADC-DAC chip is 2.36 W with a 4.2 V power supply. The ADC-DAC RFIC is packaged in a 44-pin CLLC package and achieves a peak spurious free dynamic range (SFDR) of 30.5 dBc and a peak effective number of bits (ENOB) of 2.8 bits at a 20 GS/s sampling rate.

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What this paper is about

A 3-bit analog-to-digital converter (ADC) for software defined radio applications that can work at a sampling rate of 20 GS/s is presented in this paper. In order to operate at Ku-band, two flash current mode logic (CML) ADCs are time-interleaved to achieve a 20 GHz sampling rate. A 3-bit current-steering digital-to-analog converter (DAC) is also designed for testing the high-speed ADC. The ADC-DAC RFIC is implemented in a 0.12 mum SiGe technology and occupies an area of 1.5 times 1.7 mm2. The total power consumption for the entire ADC-DAC chip is 2.36 W with a 4.2 V power supply. The ADC-DAC RFIC is packaged in a 44-pin CLLC package and achieves a peak spurious free dynamic range (SFDR) of 30.5 dBc and a peak effective number of bits (ENOB) of 2.8 bits at a 20 GS/s sampling rate.

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Available abstract

A 3-bit analog-to-digital converter (ADC) for software defined radio applications that can work at a sampling rate of 20 GS/s is presented in this paper. In order to operate at Ku-band, two flash current mode logic (CML) ADCs are time-interleaved to achieve a 20 GHz sampling rate. A 3-bit current-steering digital-to-analog converter (DAC) is also designed for testing the high-speed ADC. The ADC-DAC RFIC is implemented in a 0.12 mum SiGe technology and occupies an area of 1.5 times 1.7 mm2. The total power consumption for the entire ADC-DAC chip is 2.36 W with a 4.2 V power supply. The ADC-DAC RFIC is packaged in a 44-pin CLLC package and achieves a peak spurious free dynamic range (SFDR) of 30.5 dBc and a peak effective number of bits (ENOB) of 2.8 bits at a 20 GS/s sampling rate.

Key concepts: Flash ADC, Spurious-free dynamic range, Effective number of bits, RFIC, Analog-to-digital converter, Electronic engineering, Electrical engineering, Software-defined radio

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