Design of 5-Bit Flash ADC Using Multiple Input Standard Cell Gates for Large Input Swing

This paper proposes the different way of designing standard-cell based flash ADC in order to increase its input dynamic range. It includes implementation of 5-bit flash ADC for fully automated digital synthesis. The input dynamic range is increased by including 5-input logic gates. The proposed architecture results in Differential Non-Linearity (DNL) of ± 0.206 LSB and Integral Non-Linearity (INL) of ± 0.218 LSB range. This standard-cell based flash ADC has Effective Number of Bits (ENOB) of 4.78 bits at the sampling frequency of 400 MS/s. The Spurious-Free Dynamic Range (SFDR) of 42.05 dB is achieved at an input frequency of 1.95 MHz.