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2011•Unpublished venueRequires access

Design and performance evaluation of on chip network with Transaction Level Modeling

Nourddine Abid, Wissem Chouchene, Brahim Attia, Abdelrim Zitouni, Rached Tourki

Open publisher page 1 citations

Abstract

Networks-On-Chip (NoC) are appropriate solutions to connect the increasing number of components being integrated into Systems-on-Chip. To simulate such systems at early design stage, abstraction techniques like Transaction Level Modeling (TLM) are used to describe the communication. In this paper, three different mesh 2D sizes are evaluated using SystemC TLM2 with a single transaction and reduced accuracy. Register Transfer Level (RTL) model and Loosely Timed (LT) Transaction Level models are compared.

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What this paper is about

Networks-On-Chip (NoC) are appropriate solutions to connect the increasing number of components being integrated into Systems-on-Chip. To simulate such systems at early design stage, abstraction techniques like Transaction Level Modeling (TLM) are used to describe the communication. In this paper, three different mesh 2D sizes are evaluated using SystemC TLM2 with a single transaction and reduced accuracy. Register Transfer Level (RTL) model and Loosely Timed (LT) Transaction Level models are compared.

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Available abstract

Networks-On-Chip (NoC) are appropriate solutions to connect the increasing number of components being integrated into Systems-on-Chip. To simulate such systems at early design stage, abstraction techniques like Transaction Level Modeling (TLM) are used to describe the communication. In this paper, three different mesh 2D sizes are evaluated using SystemC TLM2 with a single transaction and reduced accuracy. Register Transfer Level (RTL) model and Loosely Timed (LT) Transaction Level models are compared.

Key concepts: SystemC, Transaction-level modeling, Computer science, Database transaction, Abstraction, Network on a chip, System on a chip, Electronic system-level design and verification

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