High level modeling of physical layer noise parameters using SystemC

SystemVerilog and SystemC are extensively used for design and Verification in VLSI industry. This paper propose a method to combine SystemVerilog and SystemC code in a single hardware/software simulation which allows design teams to leverage abstract representations of system function as it increases system simulations speed. Both languages interoperate through an intermediate layer of abstraction known as Transaction Level Models (TLMs). This paper develops Universal Verification Methodology (UVM) TLM environment for SV and SC communication in the system modeling.